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Orderly Deposition of Uncontaminated Graphene





Xiaogan Liang of Berkeley Lab has invented an inexpensive, high-throughput process for depositing pure few-layer-graphene (FLG) in a desired pattern onto substrates, such as silicon wafers. This method uses electrostatic forces to print FLG in dimensions ranging from less than 20 nm to 100 mm and has the potential to be combined with step-and-repeat technology to cover large areas.

In the Berkeley Lab technology, the desired pattern is created on the pristine surface of a highly oriented pyrolytic graphite (HOPG) stamp. The stamp is brought into contact with the substrate, and one to three layers of graphene are deposited with great accuracy by the application of electrostatic forces. The stamp is removed and the graphene remains bonded to the substrate by van de Waals forces alone.

The invention was used to create 1.4 mm pillars and 18 nm-wide nanolines of FLG on SiO2/Si substrates. These structures were visualized with scanning electron microscopy and atomic force microscopy, and their graphene composition was confirmed with Raman spectroscopy. The nanolines were used to create transistors that had excellent transport properties with highly mobile holes and electrons. The rapid current in the FLG nanolines and nanoribbons and their high sensitivity to electric fields may also allow for applications in biosensors, antennae, and photovoltaics.

Graphene offers significant advantages over silicon as a potential semiconductor because of its exceptional electronic properties: high carrier mobility, stable 2D structure, and the potential to enable scatter-free electron movement at room temperature. However, several obstacles have prevented graphene from being used for commercial electronics. Primarily, it is difficult to deposit graphene in a precise and electronically useful pattern over the relatively large (6 in., 8 in., or 12 in.) surface of a standard silicon wafer or other substrate. Current methods such as epitaxial growth, adhesive application, and reactive deposition are either expensive or risk contamination of the deposited material. The Berkeley Lab technology overcomes these limitations to make graphene a viable semiconductor material.

DEVELOPMENT STAGE: Proof of principle achieved.

STATUS: Published US Patent Application 12/630,989 available at Available for licensing or collaborative research.

Liang X., A.S.P. Chang, Y. Zhang, B.D. Harteneck, H. Choo, D.L. Olynick, S. Cabrini. “Electrostatic force assisted exfoliation of prepatterned few-layer graphenes into device sites,” Nano Lett. 9(1):467-72 (2009).


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Atomically Flat Crystal Surfaces, IB-2549

Fabrication of Uniform and Spatially Controlled Nanostructures on Substrate, IB-1997

Controlled Assembly of Nanocrystal/Organic Composites, IB-1941

Nanocrystal Heterostructures for Biological Imaging and Electronic & Photonic Devices, IB-1949


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Last updated: 08/26/2010