SC08 Workshop — Sunday, Nov. 16, 2008, Room 16A/16B
Power Efficiency and the Path to Exascale Computing
Abstracts
8:30–9:00 am
Overview of Exascale Architecture Challenges
Thomas Sterling
9:00–9:30 am
HPC Performance Limits and CMOS Maturity
Erik DeBenedictis
We will discuss the well-studied path for the maturation of CMOS in the next dozen years and the implications to computers in their current form. While continued shrinkage of microelectronics in accordance with Moore's Law looks like it will continue for some time, power efficiency and speed (clock rate) are destined to asymptotically approach physical limits. Since the architecture of the ubiquitous microprocessor requires balanced growth of many parameters to achieve an overall performance gain, microprocessor speed improvements are in serious jeopardy. We will discuss these limits and some disruptive changes that could restore performance growth.
9:30–10:00 am
Challenges in Energy Efficient Memory Architecture
Dean Klein
DRAM architecture will have an enormous impact on power consumption in tomorrow's HPC systems. This talk explores the power and performance limitations of existing memory architectures, evolutionary expectations of DDR3 and DDR4, voltage scaling and possible revolutionary approaches to memory. The impact of NAND flash and other NVM technologies will be discussed as well.
10:30–11:00 am
Energy Efficiency Challenges for Exascale Computing
Alan Gara
With energy efficiency being likely the strongest constraint as we march toward exascale, we need to understand how technology will scale to enable and invest in the appropriate technology areas. There has been much focus on the scalability of silicon.This cannot be characterized as a single number. Additionally, there are critical non-silicon areas where a significant fraction of the power is spent. The multiple components of power will be discussed as well as their scaling properties with an eye toward the exascale. This leads us to a better understanding of not only the critical technologies but also aspects of the architecture that will likely change significantly, thereby imposing new "realities" on the application users to effectively utilize future exascale machines.
11:00–11:30 am
Building Effective, Power-efficient Systems over the Next Decade
Steve Scott
Scaling to the Exaflop over the next decade will present a number of major challenges. Chief amongst these are power, reliability and programming. The Exaflop will be the last—not just the next—factor of 1000 we achieve using CMOS and traditional models of computation. This talk will present Cray's near-term approach to scaling, as well as some thoughts about what may be required in the endgame to reach this final frontier.
1:30–2:00 pm
Programming Model Challenges for Managing Massive Concurrency
Katherine Yelick
2:00–2:30 pm
Energy Aware Algorithms at the Exascale
Padma Raghavan
3:30–4:00 pm
Designing Data Centers for Future Cloud Applications
Dan Reed
4:00–4:30 pm
Towards Real-World HPC Energy Efficiency and Productivity Metrics in a Fully Instrumented Datacenter
Andres Marquez
Pacific Northwest National Laboratory has established the Energy Smart Datacenter Testbed Facility: a fully instrumented datacenter capable of monitoring power and cooling infrastructure under HPC real-world conditions, from the chip to the water tower. The multi-scale monitoring capabilities are already providing new insights into the trade-offs between the cooling chain components and their associated power consumption. More importantly, the power consumption can now be directly attributed by means of power- and thermal-signatures to different phases of high performance applications under test, including computational chemistry and weather codes. In collaboration with the “The Green Grid,” this research is driving a new generation of datacenter productivity and energy efficiency metrics that will be relevant to the HPC community.